• DocumentCode
    549657
  • Title

    Capacity optimized NoC for multi-mode SoC

  • Author

    Walter, Isask´har ; Kantor, Erez ; Cidon, Israel ; Kutten, Shay

  • Author_Institution
    Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
  • fYear
    2011
  • fDate
    5-9 June 2011
  • Firstpage
    942
  • Lastpage
    947
  • Abstract
    Network-on-Chip (NoC) is an evolving interconnection architecture addressing the rising complexity of system-on-chips (SoCs). We present a model for the cost of a NoC for a multiple use-case SoC, i.e., a system with distinct modes of operation, each having a unique traffic pattern. Specifically, we formulate an optimization problem capturing the fact that different use-cases can share capacity. We evaluate the proposed scheme using synthetic and real-life traffic, showing a substantial reduction of up to 27% in the required NoC resources, both when using a new algorithm we present and when using (a somewhat heavier) simulated-annealing procedure.
  • Keywords
    network-on-chip; simulated annealing; NoC; multimode SoC; network-on-chip; optimization problem; simulated-annealing procedure; system-on-chips; Bandwidth; Complexity theory; Optimization; Routing; Switches; System-on-a-chip; Wires; Network on-Chip; Routing; System on-Chip; Use-Cases;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
  • Conference_Location
    New York, NY
  • ISSN
    0738-100x
  • Print_ISBN
    978-1-4503-0636-2
  • Type

    conf

  • Filename
    5982015