DocumentCode
549684
Title
Aggressively scaled high-k last metal gate stack with low variability for 20nm logic high performance and low power applications
Author
Hyun, S. ; Han, J. -H ; Park, H. -B ; Na, H. -J ; Son, H.J. ; Lee, H.Y. ; Hong, H. -S ; Lee, H. -L ; Song, J. ; Kim, J.J. ; Lee, J. ; Jeong, W.C. ; Cho, H.J. ; Seo, K.I. ; Kim, D.-W. ; Sim, S.P. ; Kang, S.B. ; Sohn, D.K. ; Choi, Siyoung ; Kang, Hokyu ; Ch
Author_Institution
Semicond. R&D Center, Samsung Electron., Hwasung, South Korea
fYear
2011
fDate
14-16 June 2011
Firstpage
32
Lastpage
33
Abstract
An aggressively scaled high-k last metal gate (HKMG) stack was successfully implemented for 20nm high performance and low power applications and even below. Key technologies include aggressive Tinv scaling down to 1.1nm with new HK, suppression of Vfb roll-off, metal layer control for Vt and its excellent uniformity, and metal gate stress engineering for performance improvement.
Keywords
logic gates; low-power electronics; HKMG stack; logic; low-power applications; metal gate stress engineering; metal layer control; scaled high-k last metal gate stack; size 20 nm; Logic gates; MOS devices; Metals; Process control; Strain; Stress; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4244-9949-6
Type
conf
Filename
5984618
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