Author :
Veloso, A. ; Ragnarsson, L. -Å ; Cho, M.J. ; Devriendt, K. ; Kellens, K. ; Sebaai, F. ; Suhard, S. ; Brus, S. ; Crabbe, Y. ; Schram, T. ; Rohr, Eduardo ; Paraschiv, V. ; Eneman, G. ; Kauerauf, T. ; Dehan, M. ; Hong, S.-H. ; Yamaguchi, S. ; Takeoka, S. ; H
Abstract :
We report on gate-last technology for improved effective work function tuning with ~200meV higher p-EWF at 7Å EOT, ~2× higher fmax performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1) scavenging technique yielding UT-EOT down to ~5Å is demonstrated in gate-last, with high-k deposited first, through the use of an Etch-Stop-Layer with composite nature and similar TDDB reliability to gate-first; 2) controlled alloying for EWF engineering is obtained by careful material selection and tuned metals thicknesses ratio; 3) suppression of abnormal Lgate- and Wgate-dependence on JG, EOT and NBTI for devices with both high-k and metal deposited last (Lgate≥35nm, Wgate≥80nm) demonstrates the potential for improved UT-EOT control down to small devices with this scheme.
Keywords :
CMOS logic circuits; integrated circuit reliability; radiofrequency integrated circuits; EWF engineering; NBTI; TDDB reliability; aggressively-scaled EOT logic-RF CMOS; channel stress enhancement; etch-stop-layer; gate height dependence; gate-first technology; gate-last technology; high-k deposited first; improved UT-EOT; material selection; metal intrinsic stress; scavenging technique; tuned metal thicknesses ratio; work function tuning; Hafnium compounds; High K dielectric materials; Logic gates; Silicon; Stress; Tin;
