DocumentCode
549698
Title
A 0.021 µm2 trigate SRAM cell with aggressively scaled gate and contact pitch
Author
Guillorn, M.A. ; Chang, J. ; Pyzyna, A. ; Engelmann, S. ; Glodde, M. ; Joseph, E. ; Bruce, R. ; Ott, J.A. ; Majumdar, A. ; Liu, F. ; Brink, M. ; Bangsaruntip, S. ; Khater, M. ; Mauer, S. ; Lauer, I. ; Lavoie, C. ; Zhang, Z. ; Newbury, J. ; Kratschmer, E.
Author_Institution
T.J. Watson Res. Center, IBM Res., Yorktown Heights, NY, USA
fYear
2011
fDate
14-16 June 2011
Firstpage
64
Lastpage
65
Abstract
We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 μm2 (Fig. 1). The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node. A trigate device architecture with a minimum contacted gate pitch (CGP) and minimum contacted fin pitch (CFP) of 50 nm was used as the target technology for this demonstration.
Keywords
CMOS memory circuits; SRAM chips; 6T SRAM cell; CFP; CGP; CMOS technology; aggressively-scaled gate; contacted fin pitch; contacted gate pitch; device patterning; module integration; size 10 nm; size 50 nm; trigate device architecture; Lithography; Logic gates; Optimization; Random access memory; Resists; Silicides;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4244-9949-6
Type
conf
Filename
5984634
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