Variability and technology aware SRAM Product yield maximization

This work assesses the impact of process variability such as device mismatch of two in-house FinFET and a planar technology on key figures of merit (SNM and WTP) of SRAMs - for the first time not only at cell but also at product level. We show that the statistical cell response in the very end of the tails is the key metric that determines SRAM yield, which is quite different between the SRAM cell and its array. Statistical VCC_min analysis shows that for small arrays, supply voltage in planar is limited to around 1 V, in doped Bulk-FF (BFF) to 0.9 V, while undoped SOIFF reaches 0.6 V. Meanwhile, VCC limits for array sizes are 512 Kbit at 1V for planar, 2 Mbit at 0.9 V FOR BFF, and - far ahead - at least 1 GBit at 0.7 V for undoped SOIFF devices. Supported by an A_Vt sensitivity analysis, it appears to be the introduction of full depletion that forms the prime choice criteria of that device for SRAM implementations.