Ultra-low leakage junction engineering of cell transistor by raised source/drain for logic-compatible 28-nm embedded DRAM

An ultra-low leakage junction design concept is proposed for further scaling of cell transistor for logic-compatible 28-nm embedded DRAM (eDRAM). Raised source/drain (RSD) enables to introduce graded junction to short-channel FET in order to reduce junction leakage. Furthermore, the LDD formed by thermal diffusion of dopant from in-situ phosphorus-doped RSD enables to suppress subthreshold leakage by removing LDD ion implantation that causes extra broadening of impurity atoms. We demonstrated the cell FET with 0.1-pA off-leakage at 115C without Ion degradation for fully logic-compatible 28-nm eDRAM.