A reconfiguration technique for area-efficient network-on-chip topologies

The development of modern processors today looks toward an increasing number of processor cores. Those cores are connected with a rigid structure, for example NoC (network on chip) or bus. The engineer develops the NoC taking into account the average network traffic. In consequence, sometimes, one part of the network is overloaded, and the packets are transferred with a considerable delay, but the other part is underloaded, or is scarcely used. In this publication we propose a technique, which can be used to reconfigure a NoC topology both on a local and a global scale as a reaction of the traffic change. The alteration of the network topology aims to optimize the packet delay and the throughput of the network, without overstepping the available chip area.