• DocumentCode
    549800
  • Title

    A tri-modal 20Gbps/link differential/DDR3/GDDR5 memory interface

  • Author

    Kaviani, K. ; Wu, T. ; Amirkhany, A. ; Wei, J. ; Shen, J. ; Chen, C. ; Chin, T. ; Beyene, W. ; Dressler, D. ; Gadde, V. ; Huang, C. ; Le, P. ; M, M. ; Madden, C. ; Mishra, N. ; Raghavan, L. ; Saito, K. ; Secker, D. ; Shi, X. ; Shuaeb, F. ; Srinivas, S. ;

  • Author_Institution
    Rambus Inc., Sunnyvale, CA, USA
  • fYear
    2011
  • fDate
    15-17 June 2011
  • Firstpage
    234
  • Lastpage
    235
  • Abstract
    An improved asymmetric bidirectional memory interface implemented in 40-nm CMOS process achieves 20 Gbps per data link, and can also communicate with DDR3 and GDDR5 DRAM at 1.6 Gbps and 6.4 Gbps, respectively. The low-power tri-modal high-speed interface is enabled by a continuous 1.6 GHz to 10 GHz clock generation mechanism, and substantial reuse of the circuit elements between the signaling modes, particularly at the driver output stage. In the high speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE to the memory, while in memory READ it uses a linear equalizer (LEQ) with 3dB of peaking as well as a calibrated 1-tap predictive decision feedback equalizer (prDFE). The interface consisting of 16 data links achieves efficiency of better than 5.3 mW/Gbps.
  • Keywords
    CMOS memory circuits; DRAM chips; computer interfaces; equalisers; low-power electronics; CMOS process; DDR3 DRAM; GDDR5 DRAM; asymmetric bidirectional memory interface; bit rate 1.6 Gbit/s; bit rate 20 Gbit/s; bit rate 6.4 Gbit/s; circuit element reuse; data link; driver output stage; high speed differential mode; linear equalizer; low-power trimodal high-speed interface; memory READ; memory WRITE; predictive decision feedback equalizer; signaling mode; size 40 nm; transmit equalizer; trimodal differential-DDR3-GDDR5 memory interface; Clocks; Delay; Multiplexing; Phase locked loops; Random access memory; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Type

    conf

  • Filename
    5986052