A 3.6GHz 1MHz-bandwidth ΔΣ fractional-N PLL with a quantization-noise shifting architecture in 0.18µm CMOS

This paper presents a 3.6GHz ΔΣ fractional-N phase-locked loop (FNPLL) with a quantization-noise shifting (QNS) architecture. The proposed design decreases the amount of the quantization error while effectively increases the modulating frequency; hence, shifting the quantization noise to higher frequency and lower level. Fabricated in a 0.18μm CMOS, the FNPLL achieves -120dBc/Hz at 3MHz offset, with a bandwidth of 1MHz. Measurement results show up to 30dB improvement on quantization noise when QNS mode is activated.