DocumentCode
549848
Title
Electrical monitoring of gate and active area mask misalignment error
Author
Bansal, Aditya ; Singhee, Amith ; Acar, Emrah ; Costrini, Greg
Author_Institution
Thomas J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
fYear
2011
fDate
15-17 June 2011
Firstpage
220
Lastpage
221
Abstract
A model-free, gate-diffusion (PC-RX) misalignment monitor circuit is implemented in 32nm CMOS for fabrication tool and layout ground rule characterization. It requires only DC current measurements compared to existing optical methods that require special microscopy equipment. An on-chip circuit is also designed to convert misalignment to digital data to enable post-Si repair.
Keywords
CMOS digital integrated circuits; SRAM chips; monitoring; CMOS; DC current measurements; SRAM cell; active area mask misalignment error; electrical monitoring; layout ground rule characterization; model-free gate-diffusion misalignment monitor circuit; on-chip circuit; optical methods; size 32 nm; Current measurement; Decoding; FETs; Fabrication; Layout; Logic gates; Optical variables measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986114
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