DocumentCode
549887
Title
A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance
Author
Kim, Jung Pill ; Kim, Taehyun ; Hao, Wuyang ; Rao, Hari M. ; Lee, Kangho ; Zhu, Xiaochun ; Li, Xia ; Hsu, Wah ; Kang, Seung H. ; Matt, Nowak ; Yu, Nick
Author_Institution
Qualcomm Inc., San Diego, CA, USA
fYear
2011
fDate
15-17 June 2011
Firstpage
296
Lastpage
297
Abstract
1Mb embedded STT-MRAM macro using 45nm CMOS process includes two key design features; a dual-voltage row decoder with a charge sharing scheme for read operations and a sensing circuit with two equalizers and read-disturbance-free reference cells. These designs minimize read-disturbance and achieve fast read operation.
Keywords
CMOS memory circuits; MRAM devices; equalisers; integrated circuit design; CMOS process; charge sharing scheme; dual-voltage row decoder; embedded STT-MRAM; equalizers; read-disturbance-free reference cells; sensing circuit; size 45 nm; Arrays; Decoding; Monte Carlo methods; Semiconductor device measurement; Sensors; Tunneling magnetoresistance; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986428
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