Optimal design of the serial data receiving path

Using the Finite State Machines (FSMs) as the core control unit, a serial data receiving scheme based on FPGA is proposed in this paper. The scheme adopts FPGA instead of dedicated chips in digital system to implement asynchronous serial data receiving, and then, to identify and check the data packet in accordance with a certain format. The FSMs described following the coding guidelines of Hardware Description Language (HDL) are introduced to control each module. The design simplifies the circuits, reduces volume, increases data reliability, and more over, processes the data packet by hardware which lightens the processor´s calculation load, thus improving digital system´s performance. Simulation and practical testing are carried out at last. The results show that the data receiving is accurate and reliable which validates the validity of the design.