Title :
Parametric study of dead time effect on three phase AC output impedance of Voltage Source Inverter (VSI)
Author :
Zhiyu Shen ; Jaksic, M. ; Ahmed, Shehab ; Mattavelli, Paolo ; Boroyevich, Dushan
Author_Institution :
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
fDate :
Aug. 30 2011-Sept. 1 2011
Abstract :
This paper reports that the output impedance of a VSI measured in experiments differs from the results derived from the traditional small-signal model known in the literature. A parametric study of this effect is conducted by simulation, and then verified by experiment. The result reveals that dead time is the main contributor to the difference in impedance between simulation and experimentation. Dead time adds a resistive part to the VSI output impedance.
Keywords :
invertors; VSI; dead time effect; impedance difference; parametric study; small-signal model; three phase AC output impedance; voltage source inverter; Impedance; Impedance measurement; Inductors; Integrated circuit modeling; Load modeling; Modulation; Switches; Modeling; Voltage Source Inverters (VSI);
Conference_Titel :
Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on
Conference_Location :
Birmingham
Print_ISBN :
978-1-61284-167-0
Electronic_ISBN :
978-90-75815-15-3
