Failure modes and robustness of SiC JFET transistors under current limiting operations

Author

Bouarroudj-Berkani, M. ; Lefebvre, Serge ; Othman, D. ; Sabrine, S.M. ; Khatir, Z. ; Salah, T.B.

Author_Institution

CNAM, SATIE ENS CACHAN, Cachan, France

fYear

2011

fDate

Aug. 30 2011-Sept. 1 2011

Firstpage

1

Lastpage

10

Abstract

The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance and saturation current are discussed. Finally, thermal simulation results are presented in order to understand and explain evolutions of some ageing indicators.

Keywords

ageing; fault current limiters; junction gate field effect transistors; power field effect transistors; semiconductor device testing; short-circuit currents; silicon compounds; SiC; SiC JFET prototype transistor; SiC JFET transistor; ageing indicator; ageing test; current limiting operation; failure mode; on-state resistance; saturation current; short circuit mode; thermal simulation; Aging; JFETs; Junctions; Logic gates; Resistance; Silicon carbide; Current limiter; JFET; Power semiconductor; Robustness; Short circuit; Silicon Carbide;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on

Conference_Location

Birmingham

Print_ISBN

978-1-61284-167-0

Electronic_ISBN

978-90-75815-15-3

Type

conf

Filename

6020356