Modeling of simultaneous switching noise effects on jitter characteristics of delay locked loop in a hierarchical system of chip-Package-PCB

A new model is proposed to estimate simultaneous switching noises (SSNs) effects on clock jitter of delay locked loop (DLL) in a hierarchical system of chip, package and PCB. This method is to investigate the SSN coupling paths and effects on the clock jitter. It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. To validate the proposed model, DLL was fabricated using TSMC 0.18 um. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. It is confirmed that the jitter transfer function is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN.