Modeling and analysis of power supply noise effects on analog-to-digital converter in 3DIC

In this paper, the modeling and analysis of power supply noise effects on analog-to-digital converter (ADC) with chip-Package-PCB hierarchical power distribution network (PDN) is proposed. Especially, this research is focused on the PDN structure, which includes power/ground Through-Silicon-Via (TSV) for the case study of various PDN structures. The analysis was progressed with a frequency range from 1MHz to 3GHz. Analysis results indicate that ADC performance is degraded by power supply noise and it depends on PDN structures. The performance of ADC which interconnected by TSV was worse than that of ADC which interconnected by wirebond, because TSV has lower inductance than wire-bond.