Simulation of multiconductor transmission lines using block-latency insertion method and model order reduction technique

This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a model order reduction (MOR) technique. The block-LIM is one of the efficient transient analysis methods adopting an explicit leapfrog finite difference method. In the block-LIM, due to duality of voltage and current variables, they are successfully separated from each other by using a staggered time step placement. Thus, each of them can be updated individually within a local block through a time stepping procedure. In this work, we build a reduced order model of the partitioned local block to improve the efficiency of the block-LIM. Compared to other circuit partitioning techniques coupled with the MOR, the order-reduced block-LIM can easily decrease whole computational costs of the transient simulation. Numerical results show that our approach is adequate for the fast simulation of tightly coupled multiconductor transmission lines with CMOS inverters.