A fast-locking clock and data recovery circuit with a lock detector loop

This work presents a PLL-based (phase-locked loop) clock and data recovery (CDR) circuit with a lock detector loop for fast locking and low jitter. We use an adjustable charge pump to change the charge current according to the state of the lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype was implemented using a typical 0.18 μm CMOS process. The post-layout-extracted simulation results reveal that the worst case jitter of the recovery clock is less than 199.66 ps (peak-to-peak) and the settling time is less than 4 μs at all PVT (Process, voltage, and temperature) corners.