An All-Digital Despreading Clock Generator

Author

I-Ting Lee ; Shih-Han Ku ; Shen-Iuan Liu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

61

Issue

1

fYear

2014

fDate

Jan. 2014

Firstpage

16

Lastpage

20

Abstract

An all-digital despreading clock generator (DSCG) is presented. For an input spread-spectrum clock with a modulation frequency of 15-40 kHz and a down spreading of 5000 ppm, this DSCG successfully realizes a nonspread-spectrum clock. It is fabricated in a 0.18- μm CMOS process. For an input spread-spectrum clock of 1.5 GHz with a down spreading of 5000 ppm and a modulation frequency of 30 kHz, the measured root-mean-square and peak-to-peak jitters of this DSCG are 2.94 and 22.78 ps, respectively. The active area including input/output buffers is 0.84 mm². Its power consumption is 19.8 mW, for a supply of 1.8 V.

Keywords

CMOS digital integrated circuits; clocks; CMOS process; all-digital DSCG; all-digital despreading clock generator; down spreading; frequency 15 kHz to 40 kHz; input spread-spectrum clock; measured root-mean-square jitter; modulation frequency; nonspread-spectrum clock; peak-to-peak jitters; power 19.8 mW; size 0.18 mum; time 2.94 ps; time 22.78 ps; voltage 1.8 V; Calibration; Clocks; Frequency measurement; Frequency modulation; Generators; Synchronization; All-digital phase-locked loop (ADPLL); despreading; spread-spectrum clock;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2013.2290913

Filename

6709748