• DocumentCode
    56172
  • Title

    SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

  • Author

    Painkras, Eustace ; Plana, Luis A. ; Garside, Jim ; Temple, Sally ; Galluppi, Francesco ; Patterson, Cameron ; Lester, David R. ; Brown, Andrew D. ; Furber, Steve B.

  • Author_Institution
    Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
  • Volume
    48
  • Issue
    8
  • fYear
    2013
  • fDate
    Aug. 2013
  • Firstpage
    1943
  • Lastpage
    1953
  • Abstract
    The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.
  • Keywords
    microprocessor chips; neural net architecture; parallel architectures; system-on-chip; ARM968 processor node; CMP; SpiNNaker chip multiprocessor; cost effective simulator; custom designed globally asynchronous locally synchronous system; flexible simulator; massively parallel neural network simulation; neuroscience experiment; packet switched asynchronous communications; parallel computer system; power 1 W; spiking neural network architecture; spiking neuron; synchronous island; system-on-chip; Biological system modeling; Brain modeling; Computational modeling; Hardware; Neurons; System-on-chip; Asynchronous interconnect; chip multiprocessor; energy efficiency; globally asynchronous locally synchronous (GALS); network-on-chip; neuromorphic hardware; real-time simulation; spiking neural networks (SNNs);
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2013.2259038
  • Filename
    6515159