Title :
Design and implementation of low power clock distribution network
Author :
Kulkarni, Amruta A. ; Khandekar, Prasad D.
Author_Institution :
Electronics and Telecommunication, Vishwakarma Institute of Information Technology, Pune, India
Abstract :
Clock distribution network forms an integral part of any digital circuit. It consumes a large part of the total circuit power, which is not desirable. Different techniques are employed up till now to reduce the clock power. In this paper we have demonstrated how clock power can be reduced significantly by distributing it at reduced supply voltage. The clock distribution network is designed and simulated in 0.25µm technology. It is simulated at different frequencies of 10MHz, 100MHz, 200MHz, 250 MHz and 400MHz achieving power reduction of about 53%, 44%, 41%, 24% and 5% respectively.
Keywords :
Clocks; Latches; Very large scale integration; VLSI; clock distribution network; low power;
Conference_Titel :
Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on
Conference_Location :
Nagapattinam, Tamil Nadu, India
Print_ISBN :
978-1-4673-0213-5