Implementation of full adder cells using NP-CMOS and Multi-Output logic styles in 90nm technology

Author

Reddy, K. Vasudeva ; Sravani, K. ; Kumar, N. Nagaraja

Author_Institution

ECE, SVU, Nellore, India

fYear

2012

fDate

30-31 March 2012

Firstpage

489

Lastpage

494

Abstract

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using Tanner and 90nm CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 fem to joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords

CMOS integrated circuits; adders; integrated circuit design; NP-CMOS; cell delay; dynamic logic style; full adder cells; multioutput design; multioutput logic styles; multioutput structures; power-delay product; size 90 nm; voltage 1.8 V; CMOS integrated circuits; CMOS technology; Clocks; Conferences; Power supplies; Standards; Transistors; Dynamic-Logic; Full Adder; High Speed; Multi Output; NP-CMOS; Style; Zipper;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on

Conference_Location

Nagapattinam, Tamil Nadu

Print_ISBN

978-1-4673-0213-5

Type

conf

Filename

6216052