A high speed two-stage dual-path operational amplifier in 40nm digital CMOS

This paper presents a design of a high speed operational amplifier using 40nm digital CMOS technology. The proposed two-stage dual-path fully differential topology is based on the Improved Recycling Folded Cascode (IRFC) topology. The IRFC first stage provides a moderate DC gain, and the high efficient dual-path push-pull output stage provides ultra-high unity-gain frequency bandwidth (UGBW) with relatively low power consumption. It could find wide application in high bandwidth high resolution analog-to-digital converters (ADCs). Under 1.1V supply voltage, the simulation results show that the proposed operational amplifier topology could achieve 56.3dB DC gain, 3GHz UGBW, 24.8μV RMS noise integrated from DC to 50MHz and 2.9ns settling time with 1V peak-to-peak differential input signal.