Simulation study of nanoscale double-gate CMOS circuits using compact advanced transport models

Author

Cheralathan, Muthupandian ; Contreras, Esteban ; Alvarado, Joaquín ; Cerdeira, Antonio ; Iñiguez, Benjamin

Author_Institution

DEEAE, Univ. Rovira i Virgili, Tarragona, Spain

fYear

2012

fDate

24-26 May 2012

Firstpage

74

Lastpage

77

Abstract

In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. A template device representative for a downscaled symmetric double-gate MOSFET was used to validate the model. A CMOS inverter has been analyzed. Comparison between the drift-diffusion (DD) and hydrodynamic transport model within the practical range of bias voltages has been highlighted.

Keywords

CMOS integrated circuits; MOSFET; circuit simulation; hardware description languages; invertors; CMOS inverter; DD; DG; SMASH circuit simulator; Verilog-A circuit simulation; compact advanced transport model; downscaled symmetric double-gate MOSFET; drift-diffusion; hydrodynamic transport model; nanoscale double-gate CMOS circuit; nanoscale double-gate MOSFET compact model; transient behavior electrical CMOS circuit; CMOS integrated circuits; Capacitance; Hardware design languages; Hydrodynamics; Integrated circuit modeling; MOSFET circuits; Semiconductor device modeling; Double-gate MOSFET; Hydrodynamic; SMASH; Verilog-A;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings of the 19th International Conference

Conference_Location

Warsaw

Print_ISBN

978-1-4577-2092-5

Type

conf

Filename

6226279