DocumentCode
564940
Title
A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs
Author
Zebelein, Christian ; Falk, Joachim ; Haubelt, Christian ; Teich, Jürgen
Author_Institution
Univ. of Rostock, Rostock, Germany
fYear
2012
fDate
2-3 June 2012
Firstpage
17
Lastpage
22
Abstract
High-level synthesis tools are gaining more and more acceptance in industrial design flows. While they increase productivity in implementing a single complex hardware module, synthesizing and optimizing many hardware components simultaneously is still an open problem. In particular, resource sharing is typically only performed for single components, thereby neglecting optimization possibilities across concurrent modules. On the other hand, domain-specific models and specifications, which are generally seen as a key ingredient to raise the level of abstraction in future design flows, may enable such global optimizations. In this paper, we present a model-based approach for inter-process resource sharing which provides for efficient high-level synthesis of streaming applications modeled as a set of communicating processes. The applicability of the proposed approach is validated by a case study.
Keywords
data flow graphs; high level synthesis; optimisation; system-on-chip; MPSoC synthesis; concurrent module; dataflow graphs; domain-specific model; domain-specific specification; global optimizations; hardware component optimization; hardware component synthesis; high-level synthesis tool; industrial design flow; model-based interprocess resource sharing approach; single-complex hardware module; streaming applications; Computational modeling; Delay; Multiplexing; Optimization; Pipelines; Registers; Resource management;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic System Level Synthesis Conference (ESLsyn), 2012
Conference_Location
San Francisco, CA
ISSN
2117-4628
Print_ISBN
978-1-4673-1630-9
Electronic_ISBN
2117-4628
Type
conf
Filename
6240591
Link To Document