Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors

We have designed and fabricated double-gate ambipolar field-effect transistors, which exhibit p-type and n-type characteristics by controlling the polarity of the second gate. In this work, we present an approach for designing an efficient regular layout, called Sea-of-Tiles (SoTs). First, we address gate-level routing congestion by proposing compact layout techniques and novel symbolic-layout styles. Second, we design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks on the SoT. Our study shows that SoT with Tile_G2 and TileG_1h2, on an average, outperforms the one with Tile_G1 and Tile_G3 by 16% and 10% in area utilization, respectively.