• DocumentCode
    565120
  • Title

    Physics matters: Statistical aging prediction under trapping/detrapping

  • Author

    Velamala, Jyothi Bhaskarr ; Sutaria, Ketul ; Sato, Takashi ; Cao, Yu

  • Author_Institution
    Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
  • fYear
    2012
  • fDate
    3-7 June 2012
  • Firstpage
    139
  • Lastpage
    144
  • Abstract
    Randomness in Negative Bias Temperature Instability (NBTI) process poses a dramatic challenge on reliability prediction of digital circuits. Accurate statistical aging prediction is essential in order to develop robust guard banding and protection strategies during the design stage. Variations in device level and supply voltage due to Dynamic Voltage Scaling (DVS) need to be considered in aging analysis. The statistical device data collected from 65nm test chip shows that degradation behavior derived from trapping/detrapping mechanism is accurate under statistical variations compared to conventional Reaction Diffusion (RD) theory. The unique features of this work include (1) Aging model development as a function of technology parameters based on trapping/detrapping theory (2) Reliability prediction under device variations and DVS with solid validation with using 65nm statistical silicon data (3) Asymmetric aged timing analysis under NBTI and comprehensive evaluation of our framework in ISCAS89 sequential circuits. Further, we show that RD based NBTI model significantly overestimates the degradation and TD model correctly captures aging variability. These results provide design insights under statistical NBTI aging and enhance the prediction efficiency.
  • Keywords
    CMOS digital integrated circuits; ageing; integrated circuit reliability; power aware computing; random processes; sequential circuits; statistical analysis; DVS; ISCAS89 sequential circuits; RD-based NBTI model; TD model; asymmetric aged timing analysis; circuit design; degradation behavior; device level variations; digital circuit reliability prediction; dynamic voltage scaling; guard banding strategy; negative bias temperature instability process randomness; prediction efficiency enhancement; protection strategy; reaction diffusion theory; size 65 nm; statistical aging prediction; statistical device data; statistical silicon data; supply voltage variations; technology parameters; test chip; trapping/detrapping methods; Aging; Data models; Delay; Integrated circuit modeling; Predictive models; Stress; Dynamic Voltage Scaling; Hole Trapping; Negative Bias Temperature Instability; Timing Violations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4503-1199-1
  • Type

    conf

  • Filename
    6241502