Software controlled cell bit-density to improve NAND flash lifetime

Author

Jimenez, Xavier ; Novo, David ; Ienne, Paolo

Author_Institution

Sch. of Comput. & Commun. Sci., Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland

fYear

2012

fDate

3-7 June 2012

Firstpage

229

Lastpage

234

Abstract

Hybrid flash architectures combine static partitions in Single Level Cell (SLC) mode with partitions in Multi Level Cell (MLC) mode. Compared to MLC-only solutions, the former exploits fast and short random writes while the latter brings large capacity. On the whole, one achieves an overall tangible performance improvement for a moderate extra cost. Yet, device lifetime is an important aspect often overlooked. In this paper, we show how a dynamic SLC-MLC scheme provides significant lifetime improvement (up to 10 times) at no cost compared to any classic static SLC-MLC partitioning based on any state of the art Flash Translation Layer policy.

Keywords

electronic engineering computing; flash memories; memory architecture; performance evaluation; NAND flash lifetime; SLC mode; device lifetime; dynamic SLC-MLC scheme; fast random writes; flash translation layer policy; hybrid flash architecture; lifetime improvement; multilevel cell mode; performance improvement; short random writes; single level cell mode; software controlled cell bit density; Ash; Benchmark testing; Computer architecture; Microprocessors; Performance evaluation; Programming; Resource management; FTL; Flash Endurance; MLC; NAND Flash Memory; SLC;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

978-1-4503-1199-1

Type

conf

Filename

6241515