Alternate hammering test for application-specific DRAMs and an industrial case study

Author

Rei-Fu Huang ; Hao-Yu Yang ; Chao, Mango C.-T. ; Shih-Chin Lin

Author_Institution

MediaTek Inc., Hsinchu, Taiwan

fYear

2012

fDate

3-7 June 2012

Firstpage

1012

Lastpage

1017

Abstract

This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.

Keywords

DRAM chips; fault diagnosis; integrated circuit design; integrated circuit testing; system-on-chip; DRAM-access frequency; alternate hammering test; application-specific DRAM; eDRAM macro; industrial DRAM arrays; memory test algorithm; pairwise word-line hammering fault detection; potential fault sites; storage-application SoC; Biological system modeling; Capacitors; Couplings; Current measurement; Layout; Random access memory; Voltage measurement; embedded-DRAM; hammering test;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

978-1-4503-1199-1

Type

conf

Filename

6241628