TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation

Three-dimensional integration based on die/wafer stacking and through-silicon-vias (TSVs) promises to overcome interconnect bottlenecks for nanoscale integrated circuits (ICs). However, TSVs are prone to defects such as shorts and opens that affect circuit operation in stacked ICs. We analyze the impact of open defects on TSVs and describe techniques for screening such defects. The proposed characterization technique estimates the additional delay introduced due to a resistive open defect as well as due to rerouting based on spare TSVs. We also present an optimization method based on integer linear programming (ILP) that allocates spares to functional TSVs such that the spare for a functional TSV is neither too close to a functional TSV (to avoid the case of both functional and spare TSV being defective) nor too far to ensure that the additional delay due to rerouting is below an upper limit. Results are presented using Hspice simulations based on a 45 nm predictive technology model, recently published data on TSV parasitics, and a commercial ILP solver.