Small delay testing for TSVs in 3-D ICs

Author

Shi-Yu Huang ; Yu-Hsiang Lin ; Kun-Han Tsai ; Wu-Tung Cheng ; Sunter, S. ; Yung-Fa Chou ; Ding-Ming Kwai

Author_Institution

Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2012

fDate

3-7 June 2012

Firstpage

1031

Lastpage

1036

Abstract

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter´s threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

Keywords

SPICE; approximation theory; delay circuits; design for testability; electrical faults; integrated circuit testing; integrated logic circuits; three-dimensional integrated circuits; threshold logic; 3D IC; SPICE simulation; TSV; VOT technique; delay fault; delay test scheme; inverter threshold; propagation delay approximation; resistive open defect; testable oscillation ring structure; through-silicon vias; variable output thresholding; Capacitance; Circuit faults; Clocks; Delay; Inverters; Resistance; Through-silicon vias; 3D IC; Design for Testability; Small Delay Testing; TSV Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

ISSN

0738-100X

Print_ISBN

978-1-4503-1199-1

Type

conf

Filename

6241631