• DocumentCode
    565255
  • Title

    Reversible statistical max/min operation: Concept and applications to timing

  • Author

    Sinha, Debjit ; Visweswariah, Chandu ; Venkateswaran, Natesan ; Xiong, Jinjun ; Zolotov, Vladimir

  • Author_Institution
    Syst. & Technol. Group, IBM, Hopewell Junction, NY, USA
  • fYear
    2012
  • fDate
    3-7 June 2012
  • Firstpage
    1067
  • Lastpage
    1073
  • Abstract
    The increasing significance of variability in modern sub-micron manufacturing process has led to the development and use of statistical techniques for chip timing analysis and optimization. Statistical timing involves fundamental operations like statistical-add, sub, max and min to propagate timing information (modeled as random variables with known probability distributions) through a timing graph model of a chip design. Although incremental timing during optimization updates timing information of only certain parts of the timing-graph, lack of established reversible statistical max or min techniques forces more-than-required computations. This paper describes the concept of reversible statistical max and min for correlated Gaussian random variables, and suggests potential applications to statistical timing. A formal proof is presented to establish the uniqueness of reversible statistical max. Experimental results show run-time savings when using the presented technique in the context of chipslack computation during incremental timing optimization.
  • Keywords
    Gaussian processes; graph theory; integrated circuit design; integrated circuit manufacture; minimax techniques; statistical analysis; statistical distributions; timing circuits; chip design; chip timing analysis; chip timing optimization; chipslack computation; correlated Gaussian random variables; incremental timing optimization; probability distributions; reversible statistical max-min operation; statistical max techniques; statistical min techniques; statistical techniques; statistical timing; submicron manufacturing process; timing graph model; timing information propagation; Accuracy; Computational modeling; Context; Logic gates; Optimization; Random variables; Timing; Statistical timing; variability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4503-1199-1
  • Type

    conf

  • Filename
    6241637