DocumentCode
565267
Title
Assessing the performance limits of parallelized near-threshold computing
Author
Pinckney, Nathaniel ; Sewell, Korey ; Dreslinski, Ronald G. ; Fick, David ; Mudge, Trevor ; Sylvester, Dennis ; Blaauw, David
Author_Institution
EECS Dept., Univ. of Michigan, Ann Arbor, MI, USA
fYear
2012
fDate
3-7 June 2012
Firstpage
1143
Lastpage
1148
Abstract
Supply voltage scaling has stagnated in recent technology nodes, leading to so-called “dark silicon.” In this paper, we investigate the limit of voltage scaling together with task parallelization to maintain task completion latency. When accounting for parallelization overheads, minimum task energy is obtained at “near threshold” supply-voltages across 6 commercial technology nodes and provides 4X improvement in overall CMP performance.
Keywords
microprocessor chips; parallel processing; power aware computing; CMP performance; dark silicon; minimum task energy; parallelization overhead; parallelized near-threshold computing; performance limit assessment; supply voltage scaling; task completion latency; task parallelization; Benchmark testing; Clocks; Delay; Energy efficiency; Logic gates; Threshold voltage; Transistors; Near-Threshold Computing; low-power design; parallelization;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-4503-1199-1
Type
conf
Filename
6241649
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