Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues

The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device configurations such as raised source/drain and FinFET may further exacerbate the PC-CA dielectric reliability. SRAM yield loss and functional stress failures of both SRAM and DRAM chips due to middle-of-line (MOL) PC-CA shorts and early breakdown have been observed during the course of technology development at 32nm. Therefore, the leakage and breakdown of middle-of-line (MOL) PC-to-CA dielectric is rapidly becoming an emerging reliability issue for a successful technology development. In this paper, a comprehensive investigation of MOL PC-to-CA reliability issues at 32nm technology node was conducted. A new qualification methodology was developed to assure PC-to-CA reliability at an acceptable level.