NiosII custom instruction on FIR filter arithmetic

According to the principle of FIR filter, we firstly design and simulate the model file with DSP Builder in the environment of Matlab/Simulink. Secondly, we transform this model file to VHDL source codes with Signal-Compiler and implement processes of analysis, synthesis and adaptation in Quartus II. At last, we create a SOPC system-NiosII, where FIR filter arithmetic can be generated to a custom instruction. Till now, the hardware-software co-design of FIR filter arithmetic has been completed.