A novel reconfigurable logic device base on 3D stack technology

In recent years, as the VLSI process scale had been developed into deep sub-micro dimension, the problem of the routing delay becomes critical. Especially for reconfigurable logic devices (RLDs) like Field Programmable Gate Arrays (FPGAs), the routing resources occupy approximately 90% of area and delay performance. In this paper, we propose a novel 3D routing architecture based on building 3D connections on the input and output pins of Logic Block to improve routing performance of reconfigurable logic devices (RLDs). The evaluation shows that the novel RLD with two layers of 3D routing architecture reduced 51.11% on borad area than conventional 2D 4-LUT island style FPGA.