Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC

Capacitive-coupling-based simultaneously bidirectional chip-to-chip transceivers for 3DIC are presented. By employing a multi-level signaling strategy with a novel cascaded capacitor configuration, the proposed transceivers can transmit and receive data simultaneously through a single inter-chip coupling capacitor and double the throughput per interconnect without significant overheads in the circuit area and power. In this work, several design and implementation issues such as dead zones, parasitic capacitance, leakage, and coupling effects are addressed. The proposed transceivers are designed and simulated in a commercial 65nm CMOS technology.