Ultralow-power fast-transient output-capacitor-less low-dropout regulator with advanced adaptive biasing circuit

An ultra-low-power fast-transient output-capacitor-less low-dropout regulator (LDO) with advanced adaptive biasing (AAB) circuit is presented in this study. At light load, the AAB circuit only delivers 0.1 μA bias current to the amplifier to maintain the stability and reduce the quiescent current. At medium load to heavy load, the AAB circuit increases bias current to 2.5 μA for performance enhancement. A simple but effective hysteresis current comparator is proposed to eliminate the metastable region between the bias current transitions. When output voltage recovers from overshoot, the settling time at minimum load current of 1 μA is too long because of the 100-pF load capacitor. Hence, a gradually descending load current is delivered by AAB circuit for regulating output voltage from overshoot to the nominal value promptly. The proposed circuit has been implemented in a mixed-signal 0.13-μm CMOS process. From the measurement results, the proposed LDO regulates the output voltage at 0.8 V from a 1-V input with 2.9 μA quiescent current at minimum load. Output voltage could be fully recovered within 1.7 μs at a voltage spike <;120 mV where load current switches from 1 μA to 100 mA in 800 ns.