• DocumentCode
    568576
  • Title

    Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes

  • Author

    Ganeshpure, Kunal ; Kundu, Sandipan

  • Author_Institution
    Mentor Graphics Corp., Wilsonville, OR, USA
  • fYear
    2012
  • fDate
    19-21 Aug. 2012
  • Firstpage
    45
  • Lastpage
    50
  • Abstract
    With the advent of 3D stacking, thermal hotspots have emerged as a significant concern, due to challenges involved in removing heat from the intervening layers. Use of thermal through silicon vias (TSVs) to transfer heat from one layer to the next has been proposed as a hotspot mitigation technique. However, thermal TSV placement directly at the hotspots, compete with other design objectives due to higher wiring congestion at those sites. This paper presents a novel temperature aware physical design methodology which consists of using auxiliary routing known as Heat Pipes, to transfer heat away from hot regions in 3D integrated circuits. Heat Pipe is dummy routing connecting hot and cold regions in the same or different layers using interconnects and thermal TSVs that are placed opportunistically away from the congested areas. In order to evaluate hotspot temperature reduction due to Heat Pipes, a thermal model to simulate the effect of metal interconnect on heat distribution in 3D integrated circuits has been developed. Results show that the proposed solution using Heat Pipes lead to a reduction of 1 to 2 Kelvin at the hotspots. It is well known that even a small reduction in temperature of hotspots may significantly reduce the need for dynamic thermal management, often leading to large gain in system performance.
  • Keywords
    heat pipes; heat transfer; integrated circuit interconnections; thermal management (packaging); three-dimensional integrated circuits; 3D integrated circuits; 3D stacking; TSV; auxiliary routing; dummy routing; heat distribution; heat pipes; heat transfer; hotspot mitigation technique; interconnects; metal interconnect; temperature 1 K to 2 K; temperature aware physical design; temperature variation reduction; thermal hotspots; thermal management; thermal model; thermal through silicon vias; Heating; Integrated circuit interconnections; Integrated circuit modeling; Metals; Routing; Thermal resistance; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Amherst, MA
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4673-2234-8
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2012.16
  • Filename
    6296446