DocumentCode
568587
Title
RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework
Author
Shafik, Rishad A. ; Al-Hashimi, Bashir M. ; Mathew, Jimson ; Pradhan, Dhiraj ; Mohanty, Saraju P.
Author_Institution
Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
fYear
2012
fDate
19-21 Aug. 2012
Firstpage
189
Lastpage
194
Abstract
System-level reliability estimation is a crucial aspect in reliable design of embedded systems. Recently reported estimation techniques use separate measurements of power consumption and reliability to demonstrate the trade-offs between them. However, we will argue in this paper that such measurements cannot determine comparative reliability of system components with different power consumptions and hence a composite measurement of reliability and power consumption is required. Underpinning this argument, we propose a SystemC based system-level reliability analysis and estimation framework, RAEF, using a novel composite metric, power normalized reliability (PNR), defined as the ratio of reliability and power consumption. We show that PNR based estimation enables insightful reliability analysis of different system components. We evaluate the effectiveness of such estimation in RAEF using a case study of MPEG-2 decoder with four processing cores considering single-event upset (SEU) based soft error model. Using this setup, we analyze and compare PNR based estimation with existing reliability evaluations at different system hierarchies. Furthermore, we demonstrate the advantages of RAEF in assessing design choices highlighting the impact of voltage scaling and architecture allocation.
Keywords
C++ language; embedded systems; hardware description languages; integrated circuit design; integrated circuit reliability; power aware computing; power consumption; MPEG-2 decoder; PNR based estimation; RAEF; SEU; SystemC; architecture allocation; embedded system; estimation technique; power consumption; power normalized system-level reliability analysis; reliability evaluation; reliable design; single-event upset; soft error model; system component; system hierarchy; system-level reliability estimation; voltage scaling; Decoding; Estimation; Monitoring; Power demand; Registers; Reliability engineering; Low power design; System-level design; reliability estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
Conference_Location
Amherst, MA
ISSN
2159-3469
Print_ISBN
978-1-4673-2234-8
Type
conf
DOI
10.1109/ISVLSI.2012.42
Filename
6296471
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