Aging-Aware Instruction Cache Design by Duty Cycle Balancing

The degradation of CMOS devices over the lifetime can cause the severe threat to the system performance and reliability at deep sub micron semiconductor technologies. The negative bias temperature instability (NBTI) is among the most important sources of the aging mechanisms. Applying the traditional guard banding technique to address the decreased speed of devices is too costly. Due to the unbalanced duty cycle ratio of the SRAM cells, the instruction cache suffers a heavy NBTI stress and this will further exacerbate the aging effect in the instruction cache. In this paper, we propose an aging-aware design to combat the NBTI-induced aging in the instruction cache. First, the detailed lifetime behaviors of the cache lines in the instruction cache are studied. Then, different schemes are proposed to mitigate the negative aging effects by balancing the duty cycle ratio of the SRAM cells in the cache lines according to their different lifetime phases. By applying our proposed idle-time-based cache line invalidation and bit-flipping /complementing schemes, the duty cycle ratio of the instruction cache can be well balanced and the NBTI stress will be significantly reduced.