A Power Analysis Resistant DES Cryptographic Algorithm and Its Hardware Design

Author

Jie, Li ; Yuxiang, Lv ; Huafang, Sun ; Weiwei, Shan

Author_Institution

Nat. ASIC Syst. Eng. Center, Southeast Univ., Nanjing, China

fYear

2012

fDate

July 31 2012-Aug. 2 2012

Firstpage

121

Lastpage

124

Abstract

To deal with the threat of power analysis to encryption device, a new power analysis resistant DES algorithm architecture is proposed, which is combined with "asymmetric" mask technique. And its digital hardware circuit is designed. Then its power analysis attack resistant ability is tested. Compared with non-protected DES, using nearly 5 times larger samples and attack time, the key of the proposed DES still cannot be gained through correlation power analysis. Experiment results show that the designed DES algorithm has a certain anti power analysis effect.

Keywords

cryptography; logic design; antipower analysis effect; asymmetric mask technique; digital hardware circuit; encryption device; hardware design; nonprotected DES; power analysis attack resistant ability; power analysis resistant DES cryptographic algorithm; Algorithm design and analysis; Encryption; Hardware; IP networks; Mathematical model; Power demand; Correlation Power Analysis; DES; Mask Technique;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Manufacturing and Automation (ICDMA), 2012 Third International Conference on

Conference_Location

GuiLin

Print_ISBN

978-1-4673-2217-1

Type

conf

DOI

10.1109/ICDMA.2012.29

Filename

6298269