Reducing Power Consumption of Floating-Point Multiplier via Asynchronous Technique

With the expanding of large computing platforms and the increasing of on chip transistors, power consumption becomes a significant problem. Many methods are proposed in different design levels to solve the problem. In this paper, we introduce asynchronous technique to an IEEE-754 double-precision floating-point multiplier aiming to reduce its power consumption. The control path of the asynchronous multiplier employs redundant four-phase latch controllers and asymmetric delay elements. Experimental results show the power consumption of the asynchronous multiplier is at least 16% lower than its synchronous equivalent when running the PARSEC benchmarks. After synthesized in UMC 180nm technology, the area overhead of the asynchronous multiplier is 0.31%.