Reducing Transistor Variability for High Performance Low Power Chips

Author

Rogenmoser, R. ; Clark, Lawrence T.

Volume

33

Issue

2

fYear

2013

fDate

March-April 2013

Firstpage

18

Lastpage

26

Abstract

CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.

Keywords

CMOS integrated circuits; MOSFET; compensation; power aware computing; power supplies to apparatus; CMOS fabrication processes; CMOS integrated-circuit supply-voltage reduction; body factor; depleted channel transistor; environmental effects; higher-performance lower-power chips; random variability reduction; systematic variation; transistor variability reduction; transistor-threshold voltage scaling; voltage scaling; CMOS integrated circuits; Random access memory; Threshold voltage; Transistors; Voltage control; CMOS; DDC; VLSI; body bias; deeply depleted channel transistor; low power; undoped channel transistor; voltage scaling;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2013.10

Filename

6461870