Optimized software mapping for advanced driver assistance systems

In this paper, we present a novel approach for automated latency-optimized mapping of processes onto cores of NoC-based MPSoCs. During the mapping determination, the routing algorithm for packet-based communication is taken into account. The basic idea of the presented approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis. It maps the problem of conflict avoidance to forces for deriving an optimized process mapping. We present results obtained from two advanced driver assistance systems (ADAS), a traffic sign recognition and a depth map computation for a stereo camera system used for object recognition. As hardware platform we used a Tilera TILEPro64 processor system.