The anti-interference analysis and design for mode S reply communication of integrated TCAS

In order to effectively improve the reliability of Mode S reply communication of integrated TCAS, the anti-interference analysis and design for the communication circuit and receiving process are provided in this paper. The algorithms of preamble detection, DF-authentication, confidence detection of bit are realized by state machines and counters which were written with VHDL to improve the fault-tolerance. Anti-interference analysis and design for filter, modulator, demodulator, amplifier and detector is also provided to improve the reliability of communication. Finally, the anti-interference design is tested by wireless communication experiment. The result indicates that the algorithms which realized with FPGA can detect and decode Model S reply signal accurately with a certain fault-tolerant ability; the rise/fall time of pulse is less then 50ns, the jitter amplitude of signal is less than 3dB which agrees with RTCA standards for Model S reply communication.