A low power 6.2–8.3 GHz frequency synthesizer in SiGe BiCMOS for IEEE802.15.4a standard

The design of the low power fully integrated frequency synthesizer for IEEE 802.15.4a standard is presented. This work focuses on the VCO and the programmable frequency divider designs; which are the tuning range, power consumption and the speed limitation blocks of the frequency synthesizer. A novel low power, wideband, load-independent VCO architecture is introduced. The key feature of the VCO is the LC tank which is isolated from external parasitic load. Further, a low power programmable frequency divider based on the triple modulus prescalers is proposed. The triple modulus prescaler realizes three modes (N/N±1) via the phase switching between the output signals of the master/slave ECL divide-by-two stage. The novel N-1 mode is achieved by modifying the phase selector control logic. In addition, the 50% duty cycle baseband clock is derived from the divider chain. The frequency of the baseband clock is equal to 499.2 MHz, regardless of the chosen channel. The measured power dissipation of the proposed frequency synthesizer is equal to 37.7 mW from the supply voltage of 2.6 V. The measured phase noise is better than -85 dBc/MHz at 1 MHz offset frequency and reference spurs is not higher than -61.8 dBc within whole available channels.