A high performance and low energy intra prediction hardware for HEVC video decoding

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by intra prediction algorithm in HEVC decoder, and therefore reducing energy consumption of intra prediction hardware in HEVC decoder. The proposed techniques significantly reduce the amount of computations performed by 4×4 and 8×8 luminance prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance intra prediction hardware for 4×4 and 8×8 angular prediction modes including the proposed techniques for HEVC video decoding using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.