Optimal low power and scalable memory architecture for Turbo encoder

In this paper, we propose a generic SPRAM based Turbo encoder architecture, which is efficient in terms of memory and power requirements. The proposed architecture requires data memory of the size equal to the maximum block size as defined by the target standard. Proposed radix-4 (radix-2) architecture for LTE Turbo encoder is 70% (20%) more memory power efficient than other common solutions. With 40LP technology node, LTE Turbo encoder core with the proposed architecture has small foot print and low power requirements of 10.14 (6.25) K gates and 0.31 (0.51) mW at 326 MHz for radix-4 (radix-2) respectively. The proposed architecture is well suited for emerging wireless standards like LTE-advanced because the architecture is scalable for supporting simultaneous/parallel encoding of multiple data bits (higher radix) of operation for a given throughput requirement.