• DocumentCode
    580876
  • Title

    Automating timed specification transparency for human designer validation of real-time discrete-event control requirements

  • Author

    Dhananjayan, Amrith ; Seow, Kiam Tian

  • Author_Institution
    Div. of Software & Inf. Syst., Nanyang Technol. Univ., Singapore, Singapore
  • fYear
    2012
  • fDate
    20-24 Aug. 2012
  • Firstpage
    908
  • Lastpage
    913
  • Abstract
    In supervisory control of discrete-event systems, prescribing formal specifications is a non-trivial task that depends on the intuition and cognitive understanding of the designer. A human designer has no assurance if a prescribed specification is as intended, making it necessary to manually validate the specification, i.e., check whether the specification does indeed prescribe the intended requirement. This uncertainty in specification is compounded in the case of timed discrete-event systems (TDES´s), where real-timing behavior also needs to be correctly specified. The fundamental control theory for TDES´s requires a specification to be formalized as a timed transition graph (TTG), prescribing a timed regulation of logical behavior that restricts a TDES to some timed execution sequences. To help validate the specification, human designers need an algorithm that can automatically remodel the TTG specification, to highlight sequences essential for comprehending the specification´s timed restrictions while hiding irrelevant information. By `hiding´ in self-loops the associated events of all transitions deemed irrelevant to the specification, we can obtain a more comprehensible TTG, formalized by what we call a transparent TTG specification. In this paper, we propose a polynomial-time algorithm to compute TTG specifications of clear transparency.
  • Keywords
    computational complexity; discrete event systems; finite automata; formal specification; TDE; TTG specification; finite automaton; formal specifications; human designer validation; logical behavior timed regulation; polynomial-time algorithm; real-time discrete-event control requirements; supervisory control; timed discrete-event systems; timed execution sequences; timed specification transparency; timed transition graph; Algorithm design and analysis; Discrete event systems; Humans; Logic gates; Partitioning algorithms; Real-time systems; Supervisory control; Timed discrete-event systems; timed transition graph specification; transparency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Automation Science and Engineering (CASE), 2012 IEEE International Conference on
  • Conference_Location
    Seoul
  • ISSN
    2161-8070
  • Print_ISBN
    978-1-4673-0429-0
  • Type

    conf

  • DOI
    10.1109/CoASE.2012.6386316
  • Filename
    6386316